1. Field of the Invention
This invention relates to a data processor having a store buffer, more specifically, it relates to a data processor in which, even when instruction being processed by the multistage store buffer generates an exception, the exception can be processed easily.
2. Description of Related Art
In recent years, the performance of the data processor has been improved due to various improvements such as a higher operating frequency or introduction of the pipeline processing and so on.
As an exemplary data processor whose performance has been improved by introduction of the pipeline processing, it is described particularly in U.S. Pat. No. 4,402,042.
However, even when decoding and execution speed of the instructions are improved by the pipeline processing, since the processing speed of the data processor as a whole is limited by the access speed for a memory, in case the access speed for the memory is low, the improvement of the performance of the data processor is limited.
As a method for solving such problem, it is proposed to fill a gap between the access speed of a main memory whole processing speed is relatively low and the processing speed of the data processor, by buffering the instructions and data into a cache memory which is a high speed memory.
As an example of data processor utilizing the aforementioned cache memory, it is described particularly in, for example, Japanese Patent Application Laid-Open No. 63-193230 (1988).
Though the cache memory is effective in reading the instruction and data from the memory, it is problematic in storing the data in the memory. As techniques for storing data when using the cache memory, the following two are proposed.
The first method is the one called a write-back method in which only the content of the cache memory is updated and the content of the main memory is not updated immediately when the cache memory hits at writing the data, and when the content of the cache memory must be replaced, the content rewritten previously in the cache memory is also written back to the main memory.
This method is advantageous in that the data processor can execute high-speed writing of data, but there is a duration between writing the cache memory and the main memory, during which the contents of the two memories do not coincide. Therefore, such a problem is encountered that, controls related to the cache memory become complicated such as the control for preventing the operation of data which are not written back in the main memory, when accessing the main memory by a device other than the data processor which rewrites data into the cache memory, or control for writing back the entry to be replaced to the main memory when the cache memory made a miss. Also, in a video RAM in which the written data must be reflected immediately on a CRT screen, the write-back method can not be used.
The second method is the one called a write-through method in which the content of the main memory is updated immediately irrespective of the hit or miss of the cache memory when writing the data. This method is advantageous in that control of the cache memory is relatively simple and it is compatible with the video RAM. However, since data are always written in the main memory, the data processor can not execute the high-speed data writing.
Accordingly, hitherto, a method for storing the data to be written into the memory temporarily in a store buffer as a FIFO control buffer memory, so as to enable the data processor to move to the next processing before the data are written into the main memory.
As an example of the data processor using the store buffer, it is disclosed particularly in, for example, Japanese Patent Application Laid-Open No. 63-193230 (1988) and No. 1-92840 (1989), and the like.
In the data processor using the store buffer as aforementioned, even when the data storing speed is low, the processing performance of the data processor is not deteriorated.
However, in the conventional data processor, such a problem was encountered that, in the state wherein a plural number of data being processed exist in the store buffer, when a bus error occurs and the exception is detected at the storing operation of data to be stored precedingly, and further, when the instruction being executed then hits a break-point to generate the exception related to the debug, information of sufficient contents to be given to an exception processing handler can not be provided.
For example, in the data processor disclosed in Japanese Patent Application Laid Open No. 1-92840 (1989), only one logical address of the instruction being executed and saved in a stack during the exception processing is prepared. And hence, when the logical address of the instruction which generates the exception at processing of the store buffer is saved in the stack, the logical address of the instruction which generates the exception related to the debug was lost.
Also, unprocessed store data saved in the stack at exception processing and its address are only one, thus the exception occurred in the state wherein a plurality of unprocessed data are held in the store buffer can not be dealt with.
In the invention of Japanese Patent Application Laid-Open No. 63-193230 (1988), though some processing methods associated with the store buffer and the exception processing are disclosed, a reasonable solution related to the processing method of unprocessed store data is not disclosed.